1. Technical Field
The present invention generally relates to a semiconductor circuit, and more particularly, to a semiconductor integrated circuit.
2. Related Art
Semiconductor integrated circuits are fabricated by stacking a plurality of chips in order to improve the degree of integration.
As one of them, research into a via, for example, a through-silicon via (TSV) semiconductor integrated circuit has been actively conducted.
According to such a method, the plurality of chips are stacked and through-silicon vias are formed, so that all the chips are coupled to one another.
In the semiconductor integrated circuit using the through-silicon vias, various defects may occur in a fabrication process. That is, there may occur defects such as void indicating that conductive material is not filled in the through-silicon via, bump contact fail due to the bending of a chip or the movement of bump material, or crack occurring in the through-silicon via.
When such defects occur, the transferring of various signals or the supply of power may not be performed among chips, resulting in a serious operation error in the semiconductor integrated circuit.
In this regard, it is necessary to perform a repair operation according to a test for determining the occurrence of such defects and results of the test.
In a conventional art, a method has been used to check a test signal output to the outside of a semiconductor integrated circuit by using an external apparatus, and to cut a repair fuse.
However, since the semiconductor integrated circuit includes a plurality of through-silicon vias, it is necessary to observe the vias is or store a series of data by using the external apparatus and to use a repair program and the like, in order to test the occurrence of defects in the vias and repair the defects.
Therefore, in the semiconductor integrated circuit according to the conventional art, a test time and test-related data are increased, test efficiency is reduced due to the limitation of available channels and a memory of a test equipment, and a time for performing a repair operation is additionally necessary, resulting in a reduction in a fabrication yield of the semiconductor integrated circuit.